On 2023/12/20 21:59, Emil Renner Berthing wrote: > Xingyu Wu wrote: >> Add timer driver for the StarFive JH7110 SoC and select it by >> CONFIG_SOC_STARFIVE. >> >> This timer has four free-running and independent 32-bit counters. >> Each channel(counter) can trigger an interrupt when timeout even >> CPU is sleeping. So this timer is used as global timer and register >> clockevent for each CPU core after riscv-timer registration on the >> StarFive JH7110 SoC. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> >> --- >> MAINTAINERS | 7 + >> arch/riscv/Kconfig.socs | 1 + >> drivers/clocksource/Kconfig | 9 + >> drivers/clocksource/Makefile | 1 + >> drivers/clocksource/timer-jh7110.c | 360 +++++++++++++++++++++++++++++ >> include/linux/cpuhotplug.h | 1 + >> 6 files changed, 379 insertions(+) >> create mode 100644 drivers/clocksource/timer-jh7110.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 9104430e148e..fe0e803606a5 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -20617,6 +20617,13 @@ S: Maintained >> F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml >> F: sound/soc/starfive/jh7110_tdm.c >> >> +STARFIVE JH7110 TIMER DRIVER >> +M: Samin Guo <samin.guo@xxxxxxxxxxxxxxxx> > > Last time I sent a mail to samin.guo@xxxxxxxxxxxxxxxx it bounced. Was that just > a temporary error? > > /Emil Oh, This email has been deactivated and I don't have his other personal email. I had dropped it in the driver but forget it here. Will fix. Thanks, Xingyu Wu > >> +M: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> >> +S: Supported >> +F: Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml >> +F: drivers/clocksource/timer-jh7110.c >> + >> STARFIVE JH71X0 CLOCK DRIVERS >> M: Emil Renner Berthing <kernel@xxxxxxxx> >> M: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
