From: Yunfei Dong <yunfei.dong@xxxxxxxxxxxx>
Add mt8186 video decoder device nodes.
Signed-off-by: Yunfei Dong <yunfei.dong@xxxxxxxxxxxx>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
Reviewed-by: Hsin-Yi Wang <hsinyi@xxxxxxxxxxxx>
[eugen.hristev@xxxxxxxxxxxxx: minor cleanup]
Signed-off-by: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
---
I based this commit on top of the video encoder patch series.
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index ebd07bf3d9d2..e451b6c8cd9e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1959,6 +1959,43 @@ larb11: smi@1582e000 {
power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
};
+ video_decoder: video-decoder@16000000 {
+ compatible = "mediatek,mt8186-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>;
+ mediatek,scp = <&scp>;
+
+ vcodec_core: video-codec@16025000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x16025000 0 0x1000>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>,
+ <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB1_CKEN>,
+ <&topckgen CLK_TOP_UNIVPLL_D3>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
+ };
+ };
+
larb4: smi@1602e000 {
compatible = "mediatek,mt8186-smi-larb";
reg = <0 0x1602e000 0 0x1000>;
--
2.34.1
