On 12/15/2023 8:12 PM, Andrew Lunn wrote:
+ clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clockWhat exactly are you describing here? A PHY, or a PHY package? The ethernet-phy.yaml describes a PHY. So does each of your 4 PHYs have 14 clocks? The PHY package as a whole has 14*4 clocks? This seems unlikely. You have some clocks used by the package as a whole, and you have some clocks used by one specific PHY within the package. So you need a hierarchical description of the hardware in DT, to match the actual hierarchical of the hardware. This is exactly what Christian has been working on, and you have persistently ignored what he is doing. You need to work with him. Nothing is going to be merged until you and Christian have one consistent design for the two PHYs you are working on. Andrew --- pw-bot: cr
Hi Andrew, These clocks are for the whole PHY package including quad PHYs, since these clocks & resets need to be initialized at one point, i put it the previous MDIO driver code, these clocks & resets are configured after GPIO hardware reset, after these clocks and resets sequences configured, each PHY capabilities can be acquired correctly in the PHY probe function. Sorry for missing Christian's patches, i will look his patches and update qca8084 PHY driver correspondingly.
