Add Versal clocking wizard IP driver support The Versal clocking wizard is clock circuits customized to cater to clocking requirements. It provides configurable number of outputs. Datasheet link: https://docs.xilinx.com/r/en-US/pg321-clocking-wizard Changes in v5: Update the commit message register separate clock ops for versal use device match data Changes in v4: Add Ack and update subject Update changelog Fix warn Previously we had tried to upstream [1] separate driver for clocking wizard. It was decided to add support to the current driver. So abandoning the series. [1] https://lore.kernel.org/all/20221122121255.6823-1-shubhrajyoti.datta@xxxxxxx/ Changes in v3: rename the clocks to clk_in1 and s_axi_clk dt rename the clocks to clk_in1 and s_axi_clk in driver Changes in v2: rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in dt rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in driver update the warn Update the compatible to reflect versal Shubhrajyoti Datta (2): dt-bindings: clock: xilinx: add versal compatible clocking-wizard: Add support for versal clocking wizard .../bindings/clock/xlnx,clocking-wizard.yaml | 1 + drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 626 +++++++++++++++--- 2 files changed, 536 insertions(+), 91 deletions(-) -- 2.17.1
