On Tue, Dec 12, 2023 at 03:47:31AM +0000, Daniel Golle wrote: > MediaTek's USXGMII can be found in the MT7988 SoC. We need to access > it in order to configure and monitor the Ethernet SerDes link in > USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped > legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those > interface modes are also available. > > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> > --- > .../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml > > diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml > new file mode 100644 > index 0000000000000..0cdaa3545edb0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek USXGMII PCS > + > +maintainers: > + - Daniel Golle <daniel@xxxxxxxxxxxxxx> > + > +description: > + The MediaTek USXGMII PCS provides physical link control and status > + for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces > + provided by the PEXTP PHY. > + In order to also support legacy 2500Base-X, 1000Base-X and Cisco > + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to > + provide those interfaces modes on the same SerDes interfaces shared > + with the USXGMII PCS. > + > +properties: > + $nodename: > + pattern: "^pcs@[0-9a-f]+$" > + > + compatible: > + const: mediatek,mt7988-usxgmiisys > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: USXGMII top-level clock > + > + resets: > + items: > + - description: XFI reset For this two, why not just "maxItems: 1", since there are only one of each? > + > +required: > + - compatible > + - reg > + - clocks > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mediatek,mt7988-clk.h> > + #define MT7988_TOPRGU_XFI0_GRST 12 Why? You can just put the raw numbers here and avoid the issues with the bot being unable to test your series. > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + usxgmiisys0: pcs@10080000 { > + compatible = "mediatek,mt7988-usxgmiisys"; > + reg = <0 0x10080000 0 0x1000>; > + clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; > + resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>; > + }; > + }; > -- > 2.43.0
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