> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > Sent: Tuesday, December 12, 2023 4:44 PM > To: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx>; kernel@xxxxxxxx; conor@xxxxxxxxxx; robh+dt@xxxxxxxxxx; > krzysztof.kozlowski+dt@xxxxxxxxxx; paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; > mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; p.zabel@xxxxxxxxxxxxxx; emil.renner.berthing@xxxxxxxxxxxxx; Hal Feng > <hal.feng@xxxxxxxxxxxxxxxx>; Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Leyfoon Tan > <leyfoon.tan@xxxxxxxxxxxxxxxx> > Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes > > On 12/12/2023 03:58, JeeHeng Sia wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > >> Sent: Saturday, December 9, 2023 1:57 AM > >> To: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx>; kernel@xxxxxxxx; conor@xxxxxxxxxx; robh+dt@xxxxxxxxxx; > >> krzysztof.kozlowski+dt@xxxxxxxxxx; paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; > >> mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; p.zabel@xxxxxxxxxxxxxx; emil.renner.berthing@xxxxxxxxxxxxx; Hal Feng > >> <hal.feng@xxxxxxxxxxxxxxxx>; Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > >> Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Leyfoon > Tan > >> <leyfoon.tan@xxxxxxxxxxxxxxxx> > >> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes > >> > >> On 06/12/2023 12:50, Sia Jee Heng wrote: > >>> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset > >>> nodes for JH8100 RISC-V SoC. > >>> > >>> Signed-off-by: Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> > >>> Reviewed-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> > >> > >> Really? Looks automated... Care to provide any links to effects of > >> internal review? > > https://gitlab.starfivetech.com/jeeheng.sia/linux/-/commits/JH8100_Upstream/ > >> > >>> --- > >>> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++ > >>> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++ > >>> 2 files changed, 295 insertions(+) > >>> create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi > >>> > >>> diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi > >>> new file mode 100644 > >>> index 000000000000..27ba249f523e > >>> --- /dev/null > >>> +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi > >>> @@ -0,0 +1,180 @@ > >>> +// SPDX-License-Identifier: GPL-2.0 OR MIT > >>> +/* > >>> + * Copyright (C) 2023 StarFive Technology Co., Ltd. > >>> + */ > >>> + > >>> +/ { > >>> + clk_osc: clk_osc { > >> > >> No underscores in node names. > > Noted. > >> > >>> + compatible = "fixed-clock"; > >>> + #clock-cells = <0>; > >>> + clock-frequency = <24000000>; > >>> + }; > >>> + > >> > >> ... > >> > >>> diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi > >>> index f26aff5c1ddf..9863c61324a0 100644 > >>> --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi > >>> +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi > >>> @@ -4,6 +4,9 @@ > >>> */ > >>> > >>> /dts-v1/; > >>> +#include <dt-bindings/clock/starfive,jh8100-crg.h> > >>> +#include <dt-bindings/reset/starfive,jh8100-crg.h> > >>> +#include "jh8100-clk.dtsi" > >>> > >>> / { > >>> compatible = "starfive,jh8100"; > >>> @@ -357,6 +360,104 @@ uart4: serial@121a0000 { > >>> status = "disabled"; > >>> }; > >>> > >>> + syscrg_ne: syscrg_ne@12320000 { > >> > >> clock-controller@ > >> > >> Just open your bindings and take a look how it is done there... > >> > >> This applies everywhere > > I assume you did not ignore all the other comments you did not respond to. Arr, my bad. Will fix it. > > Best regards, > Krzysztof
