Re: [PATCH v4 3/4] clk: mediatek: Add pcw_chg_shift control

AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> · Mon, 11 Dec 2023 14:59:46 +0100

Il 09/12/23 22:56, Daniel Golle ha scritto:
From: Sam Shih <sam.shih@xxxxxxxxxxxx>

Introduce pcw_chg_shfit control to replace hardcoded PCW_CHG_MASK macro.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: Sam Shih <sam.shih@xxxxxxxxxxxx>
Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
---
v4: always set .pcw_chg_shift if .pcw_chg_reg is used instead of
     having an if-expression in mtk_pll_set_rate_regs().
v3: use git --from ...
v2: no changes

  drivers/clk/mediatek/clk-mt6779.c            | 1 +
  drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 1 +
  drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 1 +
  drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 1 +
  drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 1 +
  drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 1 +
  drivers/clk/mediatek/clk-pll.c               | 3 +--
  drivers/clk/mediatek/clk-pll.h               | 2 ++
  8 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
index ffedb1fe3c672..e66461f341dd3 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -1166,6 +1166,7 @@ static const struct mtk_gate apmixed_clks[] = {
  		.pcw_reg = _pcw_reg,					\
  		.pcw_shift = _pcw_shift,				\
  		.pcw_chg_reg = _pcw_chg_reg,				\
+		.pcw_chg_shift = PCW_CHG_SHIFT,				\
  		.div_table = _div_table,				\
  	}
  
diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
index 2b261c0e2b61d..184e0cd1dde29 100644
--- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c
@@ -75,6 +75,7 @@ static const struct mtk_gate apmixed_clks[] = {
  		.pcw_reg = _pcw_reg,					\
  		.pcw_shift = _pcw_shift,				\
  		.pcw_chg_reg = _pcw_chg_reg,				\
+		.pcw_chg_shift = PCW_CHG_SHIFT,				\
  		.div_table = _div_table,				\
  	}
  
diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
index 41ab4d6896a49..87c5dfa3d1ac4 100644
--- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
@@ -53,6 +53,7 @@ static const struct mtk_gate apmixed_clks[] = {
  		.pcw_reg = _pcw_reg,					\
  		.pcw_shift = _pcw_shift,				\
  		.pcw_chg_reg = _pcw_chg_reg,				\
+		.pcw_chg_shift = PCW_CHG_SHIFT,				\
  		.en_reg = _en_reg,					\
  		.pll_en_bit = _pll_en_bit,				\
  	}
diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
index 3590932acc63a..67bf5ef3f0033 100644
--- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
@@ -56,6 +56,7 @@ static const struct mtk_gate apmixed_clks[] = {
  		.pcw_reg = _pcw_reg,					\
  		.pcw_shift = _pcw_shift,				\
  		.pcw_chg_reg = _pcw_chg_reg,				\
+		.pcw_chg_shift = PCW_CHG_SHIFT,				\
  		.en_reg = _en_reg,					\
  		.pll_en_bit = _pll_en_bit,				\
  	}
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index 44a4c85a67ef5..ccd6bac7cb1fc 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -54,6 +54,7 @@ static const struct mtk_gate apmixed_clks[] = {
  		.pcw_reg = _pcw_reg,					\
  		.pcw_shift = _pcw_shift,				\
  		.pcw_chg_reg = _pcw_chg_reg,				\
+		.pcw_chg_shift = PCW_CHG_SHIFT,				\
  		.en_reg = _en_reg,					\
  		.pll_en_bit = _pll_en_bit,				\
  	}
diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c
index 9b0bc5daeac06..daddca6db44e7 100644
--- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c
@@ -39,6 +39,7 @@
  		.pcw_reg = _pcw_reg,					\
  		.pcw_shift = _pcw_shift,				\
  		.pcw_chg_reg = _pcw_chg_reg,				\
+		.pcw_chg_shift = PCW_CHG_SHIFT,				\
  		.div_table = _div_table,				\
  	}
  
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 513ab6b1b3229..139b01ab8d140 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -23,7 +23,6 @@
  #define CON0_BASE_EN		BIT(0)
  #define CON0_PWR_ON		BIT(0)
  #define CON0_ISO_EN		BIT(1)
-#define PCW_CHG_MASK		BIT(31)
  
  #define AUDPLL_TUNER_EN		BIT(31)
  
@@ -114,7 +113,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
  			pll->data->pcw_shift);
  	val |= pcw << pll->data->pcw_shift;
  	writel(val, pll->pcw_addr);
-	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
+	chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
  	writel(chg, pll->pcw_chg_addr);
  	if (pll->tuner_addr)
  		writel(val + 1, pll->tuner_addr);
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index f17278ff15d78..84bd8df13e2e5 100644
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -22,6 +22,7 @@ struct mtk_pll_div_table {
  #define HAVE_RST_BAR	BIT(0)
  #define PLL_AO		BIT(1)
  #define POSTDIV_MASK	GENMASK(2, 0)
+#define PCW_CHG_SHIFT	31
  
  struct mtk_pll_data {
  	int id;
@@ -48,6 +49,7 @@ struct mtk_pll_data {
  	const char *parent_name;
  	u32 en_reg;
  	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
+	u8 pcw_chg_shift;

Ok this is better - please call this "pcw_chg_bit" (same for the definition).

Also, since it is impossible for PCW_CHG to be 0, please add a sanity check at
the beginning of function mtk_clk_register_pll_ops(), like so:

if (!data->pcw_chg_bit) {
	pr_warn("Invalid PCW_CHG bit for pll %s", data->name);
	return ERR_PTR(-EINVAL);
}

...like that, we're fully covered for eventual mistakes during porting (etc).

Cheers,
Angelo







