The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:
socfpga_agilex.dtsi:141.20-146.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
Not tested
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index de1453a951d6..77d03caea25b 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -60,6 +60,13 @@ cpu3: cpu@3 {
};
};
+ fpga-region {
+ compatible = "fpga-region";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ fpga-mgr = <&fpga_mgr>;
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -138,13 +145,6 @@ soc {
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
- base_fpga_region {
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- compatible = "fpga-region";
- fpga-mgr = <&fpga_mgr>;
- };
-
clkmgr: clock-controller@ffd10000 {
compatible = "intel,agilex-clkmgr";
reg = <0xffd10000 0x1000>;
--
2.34.1
