On Tue, Dec 05, 2023 at 04:51:57PM +0000, Robin Murphy wrote: > Add a binding for implementations of the Arm CoreSight Performance > Monitoring Unit Architecture. Not to be confused with CoreSight debug > and trace, the PMU architecture defines a standard MMIO interface for > event counters similar to the CPU PMU architecture, where the > implementation and most of its features are discoverable through ID > registers. The implementation is separate from the CPU PMU rather than an MMIO view of it. Not really clear in my quick read of the spec. > CC: Rob Herring <robh+dt@xxxxxxxxxx> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> > CC: Conor Dooley <conor+dt@xxxxxxxxxx> > Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx> > --- > .../bindings/perf/arm,coresight-pmu.yaml | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml > > diff --git a/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml > new file mode 100644 > index 000000000000..12c7b28eee35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/arm,coresight-pmu.yaml > @@ -0,0 +1,39 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Arm Coresight Performance Monitoring Unit Architecture > + > +maintainers: > + - Robin Murphy <robin.murphy@xxxxxxx> > + > +properties: > + compatible: > + const: arm,coresight-pmu > + > + reg: > + items: > + - description: Register page 0 > + - description: Register page 1 (if dual-page extension implemented) > + minItems: 1 > + > + interrupts: > + items: > + - description: Overflow interrupt > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array Don't need a type. Already defined. > + minItems: 1 1 is always the minimum. > + description: List of CPUs with which the PMU is associated, if applicable When is it applicable? Presumably when it is associated with only a subset of CPUs? > + > + arm,64-bit-atomic: > + type: boolean > + description: Register accesses are single-copy atomic at doubleword granularity As this is recommended, shouldn't the property be the inverse. Maybe the standard 'reg-io-width = <4>' would be sufficient here? Rob
