On Fri, Dec 08, 2023 at 05:42:06PM +0800, William Qiu wrote: > Add bindings for OpenCores PWM Controller. > > Signed-off-by: William Qiu <william.qiu@xxxxxxxxxxxxxxxx> > Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Cheers, Conor. > --- > .../bindings/pwm/opencores,pwm.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml > new file mode 100644 > index 000000000000..0b85dd861dfd > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: OpenCores PWM controller > + > +maintainers: > + - William Qiu <william.qiu@xxxxxxxxxxxxxxxx> > + > +description: > + The OpenCores PTC ip core contains a PWM controller. When operating in PWM > + mode, the PTC core generates binary signal with user-programmable low and > + high periods. All PTC counters and registers are 32-bit. > + > +allOf: > + - $ref: pwm.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - starfive,jh7100-pwm > + - starfive,jh7110-pwm > + - const: opencores,pwm-v1 > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + "#pwm-cells": > + const: 3 > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + pwm@12490000 { > + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; > + reg = <0x12490000 0x10000>; > + clocks = <&clkgen 181>; > + resets = <&rstgen 109>; > + #pwm-cells = <3>; > + }; > -- > 2.34.1 >
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