On Fri, Dec 01, 2023 at 08:14:04PM +0800, Sia Jee Heng wrote: > StarFive JH8100 SoC consists of 4 RISC-V performance Cores (Dubhe-90) and > 2 RISC-V energy efficient cores (Dubhe-80). It also features various > interfaces such as DDR4, Gbit-Ether, CAN, USB 3.2, SD/MMC, etc., making it > ideal for high-performance computing scenarios. > > This patch series introduces initial SoC DTSI support for the StarFive > JH8100 SoC. The relevant dt-binding documentation has been updated > accordingly. Below is the list of IP blocks added in the initial SoC DTSI, > which can be used for booting via initramfs on FPGA: This all seems okay to me. I'll need an ack from Emil though before I can pick it up. Thanks, Conor.
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