Hi Sam,
On Sat, 2 Dec 2023 at 01:02, Sam Protsenko <semen.protsenko@xxxxxxxxxx> wrote:
>
> On Fri, Dec 1, 2023 at 10:11 AM Peter Griffin <peter.griffin@xxxxxxxxxx> wrote:
> >
> > This patch adds the compatibles and drvdata for the Google
> > gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones.
> >
> > Similar to Exynos850 it has two watchdog instances, one for
> > each cluster and has some control bits in PMU registers.
> >
> > gs101 also has the dbgack_mask bit in wtcon register, so
> > we also enable QUIRK_HAS_DBGACK_BIT.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
> > ---
> > drivers/watchdog/s3c2410_wdt.c | 47 ++++++++++++++++++++++++++++++----
> > 1 file changed, 42 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> > index 39f3489e41d6..c1ae71574457 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -68,6 +68,13 @@
> > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> >
> > +#define GS_CLUSTER0_NONCPU_OUT 0x1220
> > +#define GS_CLUSTER1_NONCPU_OUT 0x1420
> > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
> > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
> > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
> > +#define GS_RST_STAT_REG_OFFSET 0x3B44
> > +
> > /**
> > * DOC: Quirk flags for different Samsung watchdog IP-cores
> > *
> > @@ -269,6 +276,30 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> > };
> >
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 0,
> > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> > + .cnt_en_bit = 8,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
>
> Please keep it at 80 characters limit.
will fix
>
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> > + .mask_bit = 2,
> > + .mask_reset_inv = true,
> > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> > + .rst_stat_bit = 1,
> > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> > + .cnt_en_bit = 7,
> > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
>
> Please keep it at 80 characters limit.
will fix
>
> > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT,
> > +};
> > +
> > static const struct of_device_id s3c2410_wdt_match[] = {
> > { .compatible = "samsung,s3c2410-wdt",
> > .data = &drv_data_s3c2410 },
> > @@ -284,6 +315,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> > .data = &drv_data_exynos850_cl0 },
> > { .compatible = "samsung,exynosautov9-wdt",
> > .data = &drv_data_exynosautov9_cl0 },
> > + { .compatible = "google,gs101-wdt",
> > + .data = &drv_data_gs101_cl0 },
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> > @@ -604,9 +637,10 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> > }
> >
> > #ifdef CONFIG_OF
> > - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> > + /* Choose Exynos850/ExynosAutov9/gs101 driver data w.r.t. cluster index */
>
> Please keep it at 80 characters limit. Also, maybe just make it more
> generic and mention "Exynos9 platforms" instead of listing all SoCs?
>
Will fix and reword.
> Other than that:
>
> Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
Thanks!
Peter
>
>
> > if (variant == &drv_data_exynos850_cl0 ||
> > - variant == &drv_data_exynosautov9_cl0) {
> > + variant == &drv_data_exynosautov9_cl0 ||
> > + variant == &drv_data_gs101_cl0) {
> > u32 index;
> > int err;
> >
> > @@ -619,9 +653,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> > case 0:
> > break;
> > case 1:
> > - variant = (variant == &drv_data_exynos850_cl0) ?
> > - &drv_data_exynos850_cl1 :
> > - &drv_data_exynosautov9_cl1;
> > + if (variant == &drv_data_exynos850_cl0)
> > + variant = &drv_data_exynos850_cl1;
> > + else if (variant == &drv_data_exynosautov9_cl0)
> > + variant = &drv_data_exynosautov9_cl1;
> > + else if (variant == &drv_data_gs101_cl0)
> > + variant = &drv_data_gs101_cl1;
> > break;
> > default:
> > return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> > --
> > 2.43.0.rc2.451.g8631bc7472-goog
> >
