Hi Bhavya,
On 12/1/23 2:20 AM, Bhavya Kapoor wrote:
DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC
according to datasheet for J784s4.
[+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
J784s4 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf
Also looks good. (:
Reviewed-by: Judith Mendez <jm@xxxxxx>
Signed-off-by: Bhavya Kapoor <b-kapoor@xxxxxx>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index d89bcddcfe3d..b9a2358b1459 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -712,6 +712,7 @@ main_sdhci1: mmc@4fb0000 {
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
~ Judith
