On 05/12/2023 01:23, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
>
> Add bindings for the clock generator on the SG2042 RISC-V SoC.
A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
> +
> +maintainers:
> + - Chen Wang <unicorn_wang@xxxxxxxxxxx>
> +
> +properties:
> + compatible:
> + items:
Drop items, the same in previous patch. We keep simplified form for
compatibles usually.
> + - const: sophgo,sg2042-clkgen
> +
> + reg:
> + maxItems: 1
> +
> + system-ctrl:
Missing vendor prefix.
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: a phandle to SG2042 System Controller node.
Add explanation how it is used and what its purpose is.
> +
> + clocks:
> + items:
> + - description: Clock Generation IC (25 MHz)
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
> +
> +required:
> + - compatible
> + - reg
> + - system-ctrl
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@30012000 {
> + compatible = "sophgo,sg2042-clkgen";
> + reg = <0x30012000 0x1000>;
> + system-ctrl = <&sys_ctrl>;
> + clocks = <&cgi>;
> + #clock-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/sophgo,sg2042-clkgen.h b/include/dt-bindings/clock/sophgo,sg2042-clkgen.h
> new file mode 100644
> index 000000000000..b12046046f1f
> --- /dev/null
> +++ b/include/dt-bindings/clock/sophgo,sg2042-clkgen.h
> @@ -0,0 +1,169 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
> +#define __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
> +
> +/* Divider clocks */
> +#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
No indentation after #define. Open other header files and look how it is
done there.
Best regards,
Krzysztof
