This series adds the initial (clocks, pinctrl, rpmhpd, regulator, interconnect, CPU, SoC and board compatibles) device tree support to boot to shell on the Qualcomm X1E80100 platform, aka Snapdragon X Elite. Our v1 post of the patchsets adding support for Snapdragon X Elite SoC had the part number sc8380xp which is now updated to the new part number x1e80100 based on the new branding scheme and refers to the exact same SoC. V5: * Rename gcc config to CLK_X1E80100_GCC [Krzysztof/Abel/Bryan]. * Pickup Rbs. V4: * Have separate cluster_pd for each cluster. [Konrad] V3: * Add more detail to the commit msg describing Oryon. [Rob] * Add smem compatible and tcsr_hw nodes. [Abel] * Re-name l2-cache, remove hyphen in reserved region. [Konrad] * Describe certain secure gpios as unused. [Konrad] * Pickup Rbs. v2: * Update the part number from sc8380xp to x1e80100. * Fixup ordering in the SoC/board bindings. [Krzysztof] * Add pdc node and add wakeup tlmm parent. [Rajendra] * Add cpu/cluster idle states. [Bjorn] * Document reserved gpios. [Konrad] * Remove L1 and add missing props to L2. [Konrad] * Remove region suffix. [Konrad] * Append digits to gcc node. [Konrad] * Add ICC_TAGS instead of leaving it unspecified. [Konrad] * Remove double space. [Konrad] * Leave the size index of memory node untouched. [Konrad] * Override the serial uart with "qcom,geni-debug-uart" in the board files. [Rajendra] * Add additional details to patch 5 commit message. [Konrad/Krzysztof] Dependencies: clks: https://lore.kernel.org/lkml/20231117092737.28362-1-quic_sibis@xxxxxxxxxxx/ llcc: https://lore.kernel.org/lkml/20231117095315.2087-1-quic_sibis@xxxxxxxxxxx/ misc-bindings: https://lore.kernel.org/lkml/20231117105635.343-1-quic_sibis@xxxxxxxxxxx/ Release Link: https://www.qualcomm.com/news/releases/2023/10/qualcomm-unleashes-snapdragon-x-elite--the-ai-super-charged-plat Abel Vesa (1): arm64: dts: qcom: x1e80100: Add Compute Reference Device Rajendra Nayak (4): dt-bindings: arm: cpus: Add qcom,oryon compatible dt-bindings: arm: qcom: Document X1E80100 SoC and boards arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts arm64: defconfig: Enable X1E80100 SoC base configs .../devicetree/bindings/arm/cpus.yaml | 1 + .../devicetree/bindings/arm/qcom.yaml | 8 + arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 426 ++ arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 401 ++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 3527 +++++++++++++++++ arch/arm64/configs/defconfig | 3 + 7 files changed, 4368 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-qcp.dts create mode 100644 arch/arm64/boot/dts/qcom/x1e80100.dtsi -- 2.17.1
