Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> writes: > On 23/11/2023 16:26, Gregory CLEMENT wrote: >> Add a device tree include file for the Mobileye EyeQ5 SoC. >> >> Based on the work of Slava Samsonov <stanislav.samsonov@xxxxxxxxx> >> >> Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx> >> --- > > >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + }; >> + >> + cpu_intc: interrupt-controller { >> + compatible = "mti,cpu-interrupt-controller"; >> + interrupt-controller; >> + #address-cells = <0>; >> + #interrupt-cells = <1>; >> + }; >> + >> + gic: interrupt-controller@140000 { > > Why do you put MMIO nodes in top-level? I can move it back under the soc node I think > >> + compatible = "mti,gic"; >> + reg = <0x0 0x140000 0x0 0x20000>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + >> + /* >> + * Declare the interrupt-parent even though the mti,gic >> + * binding doesn't require it, such that the kernel can >> + * figure out that cpu_intc is the root interrupt >> + * controller & should be probed first. >> + */ >> + interrupt-parent = <&cpu_intc>; >> + >> + timer { >> + compatible = "mti,gic-timer"; >> + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; >> + clocks = <&core0_clk>; >> + }; >> + }; >> + >> + soc: soc { > > Are you sure dtbs_check W=1 does not complain? I think you miss here > address. Yes dtbs_check W=1 does not complain. There is no reg property in this node, so there is no address to add to the name of the node. Gregory -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com