Thank you, Krzysztof, Conor, and LeyFoon, for your comments. I will prepare version 3 to address all the feedback. > -----Original Message----- > From: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx> > Sent: Wednesday, November 29, 2023 2:01 PM > To: kernel@xxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; krzk@xxxxxxxxxx; conor+dt@xxxxxxxxxx; > paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; daniel.lezcano@xxxxxxxxxx; tglx@xxxxxxxxxxxxx; > conor@xxxxxxxxxx; anup@xxxxxxxxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; jirislaby@xxxxxxxxxx; michal.simek@xxxxxxx; Michael Zhu > <michael.zhu@xxxxxxxxxxxxxxxx>; drew@xxxxxxxxxxxxxxx > Cc: devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; JeeHeng Sia > <jeeheng.sia@xxxxxxxxxxxxxxxx>; Leyfoon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> > Subject: [PATCH v2 0/6] Initial device tree support for StarFive JH8100 SoC > > StarFive JH8100 SoC consists of 4 RISC-V performance Cores (Dubhe-90) and > 2 RISC-V energy efficient cores (Dubhe-80). It also features various > interfaces such as DDR4, Gbit-Ether, CAN, USB 3.2, SD/MMC, etc., making it > ideal for high-performance computing scenarios. > > This patch series introduces initial SoC DTSI support for the StarFive > JH8100 SoC. The relevant dt-binding documentation has been updated > accordingly. Below is the list of IP blocks added in the initial SoC DTSI, > which can be used for booting via initramfs on FPGA: > > - StarFive Dubhe-80 CPU > - StarFive Dubhe-90 CPU > - PLIC > - CLINT > - UART > > The primary goal is to include foundational patches so that additional > drivers can be built on top of this framework. > > Changes since v1: > - Dropped patch 5. > - Moved timebase-frequency from .dts to .dtsi. > - Moved soc node from .dts to .dtsi. > - Revised the title for the dt-binding document by removing Xilinx > wording. > - Added a full stop to the end of the commit messages. > - Removed extra blank lines. > - Used hyphen for a node name. > - Added more recipients to the mailing list. > > Sia Jee Heng (6): > dt-bindings: riscv: Add StarFive Dubhe compatibles > dt-bindings: riscv: Add StarFive JH8100 SoC > dt-bindings: timer: Add StarFive JH8100 clint > dt-bindings: interrupt-controller: Add StarFive JH8100 plic > dt-bindings: serial: cdns: Add new compatible string for StarFive > JH8100 UART > riscv: dts: starfive: Add initial StarFive JH8100 device tree > > .../sifive,plic-1.0.0.yaml | 1 + > .../devicetree/bindings/riscv/cpus.yaml | 2 + > .../devicetree/bindings/riscv/starfive.yaml | 5 +- > .../devicetree/bindings/serial/cdns,uart.yaml | 4 + > .../bindings/timer/sifive,clint.yaml | 1 + > arch/riscv/boot/dts/starfive/Makefile | 1 + > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ > arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++ > 8 files changed, 419 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > > base-commit: 18d46e76d7c2eedd8577fae67e3f1d4db25018b0 > -- > 2.34.1
