On Thu, Nov 30, 2023 at 06:04:51AM +0000, JeeHeng Sia wrote: > > > > -----Original Message----- > > From: Conor Dooley <conor@xxxxxxxxxx> > > Sent: Wednesday, November 29, 2023 10:46 PM > > To: JeeHeng Sia <jeeheng.sia@xxxxxxxxxxxxxxxx> > > Cc: kernel@xxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx; krzk@xxxxxxxxxx; conor+dt@xxxxxxxxxx; > > paul.walmsley@xxxxxxxxxx; palmer@xxxxxxxxxxx; aou@xxxxxxxxxxxxxxxxx; daniel.lezcano@xxxxxxxxxx; tglx@xxxxxxxxxxxxx; > > anup@xxxxxxxxxxxxxx; gregkh@xxxxxxxxxxxxxxxxxxx; jirislaby@xxxxxxxxxx; michal.simek@xxxxxxx; Michael Zhu > > <michael.zhu@xxxxxxxxxxxxxxxx>; drew@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux- > > kernel@xxxxxxxxxxxxxxx; Leyfoon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> > > Subject: Re: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles > > > > On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote: > > > Add new compatible strings for Dubhe-80 and Dubhe-90. These are > > > RISC-V cpu core from StarFive Technology and are used in StarFive > > > JH8100 SoC. > > > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx> > > > Reviewed-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx> > > > --- > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index f392e367d673..493972b29a22 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -48,6 +48,8 @@ properties: > > > - thead,c906 > > > - thead,c910 > > > - thead,c920 > > > + - starfive,dubhe-80 > > > + - starfive,dubhe-90 > > > > s goes before t. > Noted. Will fix it. With the re-order, Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Cheers, Conor.
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