On Do, 2023-11-09 at 21:52 +0000, Daniel Golle wrote: > MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to > connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R, > 2500Base-X, 1000Base-X and Cisco SGMII interface modes. > > Implement support for configuring for the new paths to SerDes interfaces > and the internal 2.5G PHY. > > Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and > setup the new PHYA on MT7988 to access the also still existing old > LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface > modes. > > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> > --- [...] > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h > index 9ae3b8a71d0e6..ba5998ef7965e 100644 > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h > @@ -15,6 +15,7 @@ > #include <linux/u64_stats_sync.h> > #include <linux/refcount.h> > #include <linux/phylink.h> > +#include <linux/reset.h> I can't see what this is required for? regards Philipp
