On 27/11/2023 01:58, Chen Wang wrote: > From: Chen Wang <unicorn_wang@xxxxxxxxxxx> > > Add bindings for the clock generator on the SG2042 RISC-V SoC. > > Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx> > --- > .../clock/sophgo/sophgo,sg2042-clkgen.yaml | 42 +++++ > include/dt-bindings/clock/sophgo-sg2042-clk.h | 169 ++++++++++++++++++ > 2 files changed, 211 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml > create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h > > diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml > new file mode 100644 > index 000000000000..6c0d0461e489 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 Clock Generator > + > +maintainers: > + - Chen Wang <unicorn_wang@xxxxxxxxxxx> > + > +properties: > + compatible: > + const: sophgo,sg2042-clkgen > + > + clocks: > + items: > + - description: Clock Generation IC (25 MHz) > + > + '#clock-cells': > + const: 1 > + description: > + See <dt-bindings/clock/sophgo-sg2042-clk.h> for valid indices. > + > + assigned-clocks: true Drop > + > + assigned-clock-rates: true Drop > + > +required: > + - compatible > + - clocks > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller { > + compatible = "sophgo,sg2042-clkgen"; Use 4 spaces for example indentation. > + clocks = <&cgi>; > + #clock-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/sophgo-sg2042-clk.h b/include/dt-bindings/clock/sophgo-sg2042-clk.h > new file mode 100644 > index 000000000000..a8e05c00c3bf > --- /dev/null > +++ b/include/dt-bindings/clock/sophgo-sg2042-clk.h The same filename as binding. > @@ -0,0 +1,169 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ Any particular reason for a bit different license than the bindings? How is your DTS licensed? > +/* > + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__ > +#define __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__ > + > +/* Divider clocks */ > +#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0 Missing tabs before each value. Best regards, Krzysztof
