Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> The timebase-frequency on PolarFire SoC is not set by an oscillator on
> the board, but rather by an internal divider, so move the property to
> mpfs.dtsi.
>
> This looks to be copy-pasta from the SiFive Unleashed as the comments
> in both places were almost identical. In the Unleashed's case this looks
> to actually be valid, as the clock is provided by a crystal on the PCB.
>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Makes sense to me.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> ---
> CC: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> CC: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
> CC: Rob Herring <robh+dt@xxxxxxxxxx>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>
> CC: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
> CC: Palmer Dabbelt <palmer@xxxxxxxxxxx>
> CC: linux-riscv@xxxxxxxxxxxxxxxxxxx
> CC: devicetree@xxxxxxxxxxxxxxx
> ---
> arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 7 -------
> arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 7 -------
> arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 7 -------
> arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts | 7 -------
> arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts | 7 -------
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 +
> 6 files changed, 1 insertion(+), 35 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> index 90b261114763..dce96f27cc89 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> @@ -8,9 +8,6 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/leds/common.h>
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define RTCCLK_FREQ 1000000
> -
> / {
> model = "Microchip PolarFire-SoC Icicle Kit";
> compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
> @@ -29,10 +26,6 @@ chosen {
> stdout-path = "serial1:115200n8";
> };
>
> - cpus {
> - timebase-frequency = <RTCCLK_FREQ>;
> - };
> -
> leds {
> compatible = "gpio-leds";
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> index 184cb36a175e..a8d623ee9fa4 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> @@ -10,9 +10,6 @@
> #include "mpfs.dtsi"
> #include "mpfs-m100pfs-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ 1000000
> -
> / {
> model = "Aries Embedded M100PFEVPS";
> compatible = "aries,m100pfsevp", "microchip,mpfs";
> @@ -33,10 +30,6 @@ chosen {
> stdout-path = "serial1:115200n8";
> };
>
> - cpus {
> - timebase-frequency = <MTIMER_FREQ>;
> - };
> -
> ddrc_cache_lo: memory@80000000 {
> device_type = "memory";
> reg = <0x0 0x80000000 0x0 0x40000000>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> index c87cc2d8fe29..ea0808ab1042 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -6,9 +6,6 @@
> #include "mpfs.dtsi"
> #include "mpfs-polarberry-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ 1000000
> -
> / {
> model = "Sundance PolarBerry";
> compatible = "sundance,polarberry", "microchip,mpfs";
> @@ -22,10 +19,6 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> - cpus {
> - timebase-frequency = <MTIMER_FREQ>;
> - };
> -
> ddrc_cache_lo: memory@80000000 {
> device_type = "memory";
> reg = <0x0 0x80000000 0x0 0x2e000000>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> index 013cb666c72d..f9a890579438 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> @@ -6,9 +6,6 @@
> #include "mpfs.dtsi"
> #include "mpfs-sev-kit-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ 1000000
> -
> / {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -28,10 +25,6 @@ chosen {
> stdout-path = "serial1:115200n8";
> };
>
> - cpus {
> - timebase-frequency = <MTIMER_FREQ>;
> - };
> -
> reserved-memory {
> #address-cells = <2>;
> #size-cells = <2>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> index e0797c7e1b35..d1120f5f2c01 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> @@ -11,9 +11,6 @@
> #include "mpfs.dtsi"
> #include "mpfs-tysom-m-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ 1000000
> -
> / {
> model = "Aldec TySOM-M-MPFS250T-REV2";
> compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
> @@ -34,10 +31,6 @@ chosen {
> stdout-path = "serial1:115200n8";
> };
>
> - cpus {
> - timebase-frequency = <MTIMER_FREQ>;
> - };
> -
> ddrc_cache_lo: memory@80000000 {
> device_type = "memory";
> reg = <0x0 0x80000000 0x0 0x30000000>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index a6faf24f1dba..266489d43912 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -13,6 +13,7 @@ / {
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> + timebase-frequency = <1000000>;
>
> cpu0: cpu@0 {
> compatible = "sifive,e51", "sifive,rocket0", "riscv";
> --
> 2.39.2
>
>
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