On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx> wrote: > > The Andes hart-level interrupt controller (Andes INTC) allows AX45MP > cores to handle custom local interrupts, such as the performance > counter overflow interrupt. > > Signed-off-by: Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - No change > --- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Cheers, Prabhakar > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > index eb301d8eb2b0..78072e80793d 100644 > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -38,7 +38,7 @@ cpu0: cpu@0 { > > cpu0_intc: interrupt-controller { > #interrupt-cells = <1>; > - compatible = "riscv,cpu-intc"; > + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; > interrupt-controller; > }; > }; > -- > 2.34.1 > >