On 11/24/2023 3:33 AM, Christian Marangi wrote:
On Thu, Nov 23, 2023 at 03:57:58PM +0100, Andrew Lunn wrote:
On Thu, Nov 23, 2023 at 02:35:31PM +0000, Russell King (Oracle) wrote:
On Thu, Nov 23, 2023 at 03:27:05PM +0100, Andrew Lunn wrote:
Just to be more precise qca807x can operate in 3 different mode:
(this is controlled by the MODE_CFG bits)
- QSGMII: 5 copper port
4 slots over QSGMII, plus the second SERDES is connected to the MAC
using SGMII/1000BaseX?
- PSGMII: 5 copper port
5 slots over QSGMII, the second SERDES is idle?
- PSGMII: 4 copper port + 1 combo (that can be both fiber or copper)
5 slots over QSGMII, with the second SERDES connected to an SFP cage.
Are ports 1-4 always connected to the P/Q SGMII. Its only port 5 which
can use the second SERDES?
I think what would really help here is if there was an ascii table to
describe the configurations, rather than trying to put it into words.
Yes.
And also for ipq4019. We need to merge these two threads of
conversation, since in the end they are probably the same driver, same
device tree etc.
For everyone that missed Robert response in patch 12 let me quote him
also here.
"
Hi Andrew,
I think that the description is confusing.
QCA807x supports 3 different modes:
1. PSGMII (5 copper ports)
2. PSGMII (4 copper ports + 1 combo port)
3. QSGMII+SGMII
So, in case option 2 is selected then the combo port can also be used for
1000Base-X and 100Base-FX modules or copper and it will autodetect the
exact media.
This is supported via the SFP op-s and I have been using it without issues
for a while.
I have not tested option 3 in combination with SFP to the copper
module so I cant
say whether that works.
For the option3, the last PHY works on SGMII mode, then it can't be
used with SFP, only copper is supported in this mode.
From what I can gather from the typical usage examples in the
datasheet, this QSMII+SGMII
mode is basically intended as a backward compatibility thing as only
QCA SoC-s have PSGMII
support so that you could still use SoC-s with QSGMII and SGMII support only.
So there is no way to control the SerDes-es individually, only the
global mode can be changed via
the Chip configuration register in the Combo port.
You can see the block diagram of this PHY in this public PDF on page 2[1].
[1] https://content.codico.com/fileadmin/media/download/datasheets/qualcomm/qualcomm_qca8075.pdf
"
