On 23.11.2023 17:53, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Mon, Nov 20, 2023 at 8:01 AM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>>
>> Hardware manual of both RZ/G2L and RZ/G3S specifies that reset monitor
>> registers need to be interrogated when the reset signals are toggled
>> (chapters "Procedures for Supplying and Stopping Reset Signals" and
>> "Procedure for Activating Modules"). Without this there is a chance that
>> different modules (e.g. Ethernet) to not be ready after reset signal is
>> toggled leading to failures (on probe or resume from deep sleep states).
>>
>> Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
>> In case you apply this patch and patch 1/13 as is, please add a Depend-on
>> tag on this patch to point to patch 1/13 for proper backporting.
>
> There is no such Depend-on tag? Anyway, this patch won't apply if 1/13
typo again... it should have been "Depends-on" which is true, it is not
documented anywhere, but I saw it is used in some commits. Maybe I should
stop using it...
> is not backported...
>
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -1416,12 +1416,23 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
>> struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
>> const struct rzg2l_cpg_info *info = priv->info;
>> unsigned int reg = info->resets[id].off;
>> - u32 value = BIT(info->resets[id].bit) << 16;
>> + u32 dis = BIT(info->resets[id].bit);
>> + u32 value = dis << 16;
>> + int ret = 0;
>>
>> dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
>>
>> writel(value, priv->base + CLK_RST_R(reg));
>> - return 0;
>> +
>> + if (info->has_clk_mon_regs) {
>> + ret = readl_poll_timeout_atomic(priv->base + CLK_MRST_R(reg), value,
>> + value & dis, 10, 200);
>> + } else {
>> + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
>> + udelay(35);
>> + }
>
> I think this should also take into account CPG_RST_MON on RZ/V2M,
> cfr. rzg2l_cpg_status().
Hm... ok, I'll have a look though it will be a bit difficult to test it ATM.
>
>> +
>> + return ret;
>> }
>>
>> static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
>> @@ -1432,12 +1443,22 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
>> unsigned int reg = info->resets[id].off;
>> u32 dis = BIT(info->resets[id].bit);
>> u32 value = (dis << 16) | dis;
>> + int ret = 0;
>>
>> dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
>> CLK_RST_R(reg));
>>
>> writel(value, priv->base + CLK_RST_R(reg));
>> - return 0;
>> +
>> + if (info->has_clk_mon_regs) {
>> + ret = readl_poll_timeout_atomic(priv->base + CLK_MRST_R(reg), value,
>> + !(value & dis), 10, 200);
>> + } else {
>> + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
>> + udelay(35);
>> + }
>
> Likewise.
>
>> +
>> + return ret;
>> }
>>
>> static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>
