Re: [PATCH V2 1/2] dt-bindings: interconnect: Add Qualcomm X1E80100 SoC

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On 11/22/23 20:22, Georgi Djakov wrote:
Hi Sibi,

Hey Georgi,

Thanks for taking time to review the series!

On 17.11.23 12:30, Sibi Sankar wrote:
From: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>

The Qualcomm X1E80100 SoC has several bus fabrics that could be controlled
and tuned dynamically according to the bandwidth demand.

Co-developed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
Co-developed-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---

v2:
* Update the part number from sc8380xp to x1e80100.
* Fixup required property ordering [Krzysztof]
* Pickup Rbs.

  .../interconnect/qcom,x1e80100-rpmh.yaml      |  83 +++++++
  .../interconnect/qcom,x1e80100-rpmh.h         | 207 ++++++++++++++++++
  2 files changed, 290 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml   create mode 100644 include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h

[..]

+#define MASTER_AV1_ENC                0
+#define MASTER_CAMNOC_HF            1
+#define MASTER_CAMNOC_ICP            2
+#define MASTER_CAMNOC_SF            3
+#define MASTER_EVA                4
+#define MASTER_MDP                5
+#define MASTER_VIDEO                6
+#define MASTER_VIDEO_CV_PROC            7
+#define MASTER_VIDEO_V_PROC            8
+#define MASTER_CNOC_MNOC_CFG            9
+#define SLAVE_MNOC_HF_MEM_NOC            10
+#define SLAVE_MNOC_SF_MEM_NOC            11
+#define SLAVE_SERVICE_MNOC            12
+#define MASTER_MDP_DISP                13
+#define SLAVE_MNOC_HF_MEM_NOC_DISP        14
+
+#define MASTER_CDSP_PROC            0
+#define SLAVE_CDSP_MEM_NOC            1
+
+#define MASTER_PCIE_NORTH            0
+#define MASTER_PCIE_SOUTH            0

This duplicate index looks like a typo?

Thanks for catching ^^. Will fix it in the next re-spin.

-Sibi


+#define SLAVE_ANOC_PCIE_GEM_NOC            3
+#define MASTER_PCIE_NORTH_PCIE            4
+#define MASTER_PCIE_SOUTH_PCIE            5
+#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE        6
[..]

Thanks,
Georgi






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