As the sg2042 uses different address for timer and mswi of its clint device, it should follow the aclint format. For the previous patchs, it only use only one address for both mtime and mtimer, this is can not be parsed by OpenSBI. To resolve this, separate these two registers in the dtb. Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc This patch can be tested with upstream SBI with the following patch: 1. https://lists.infradead.org/pipermail/opensbi/2023-November/005926.html Changed from v3: 1. add all register in the bindings Changed from v2: 1. Use reg-names to map the registers. Changed from v1: 1. change the commit to address the reason for ABI change. 2. remove unnecessary link in the commit. Inochi Amaoto (2): dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format .../timer/thead,c900-aclint-mtimer.yaml | 42 +++++++++- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++-------- 2 files changed, 89 insertions(+), 33 deletions(-) -- 2.42.1
