On 17.11.2023 12:39, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
>
> Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for
> X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers,
> geni UART, interrupt controller, TLMM, reserved memory, interconnects,
> SMMU and LLCC nodes.
>
> Co-developed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
> Co-developed-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> ---
[...]
> +&tlmm {
> + gpio-reserved-ranges = <33 3>, <44 4>, /* SPI (TPM) */
Surely SPI doesn't use 7 wires! :D
[...]
> + L2_0: l2-cache-0 {
the cache device is distinguishable by its parent, so "l2-cache" is enough
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
[...]
> + idle-states {
> + entry-method = "psci";
> +
> + CLUSTER_C4: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "ret";
> + arm,psci-suspend-param = <0x00000004>;
These suspend parameters look funky.. is this just a PSCI sleep
implementation that strays far away from Arm's suggested guidelines?
[...]
> + CPU_PD11: power-domain-cpu11 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + };
> +
> + CLUSTER_PD: power-domain-cpu-cluster {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
> + };
So, can the 3 clusters not shut down their L2 and PLLs (if separate?)
on their own?
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gunyah_hyp_mem: gunyah-hyp@80000000 {
> + reg = <0x0 0x80000000 0x0 0x800000>;
> + no-map;
> + };
> +
> + hyp_elf_package_mem: hyp-elf_package@80800000 {
no underscores in node names, use hyphens
The rest looks OK I think
Konrad
