On Fri, Nov 17, 2023 at 09:26:18AM +0530, Sibi Sankar wrote:
> On 10/25/23 22:10, Bryan O'Donoghue wrote:
> > On 25/10/2023 14:33, Sibi Sankar wrote:
> >> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> >> + .cmd_rcgr = 0x14018,
> >> + .mnd_width = 8,
> >> + .hid_width = 5,
> >> + .parent_map = gcc_parent_map_9,
> >> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> >> + .clkr.hw.init = &(const struct clk_init_data) {
> >> + .name = "gcc_sdcc2_apps_clk_src",
> >> + .parent_data = gcc_parent_data_9,
> >> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> >> + .flags = CLK_SET_RATE_PARENT,
> >> + .ops = &clk_rcg2_floor_ops,
> >
> > diff sc8280xp..sc8380xp
> >
> > Here you've used floor instead of shared ops, why is that ?
>
> We seem to use floor ops for sdcc clks on all other QC SoCs and
> sc8280xp seems to be the exception here. So I'll continue to use floor
> ops for sdcc.
> >> +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
> >> + .cmd_rcgr = 0x17158,
> >> + .mnd_width = 0,
> >> + .hid_width = 5,
> >> + .parent_map = gcc_parent_map_0,
> >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> >> + .clkr.hw.init = &(const struct clk_init_data) {
> >> + .name = "gcc_usb30_mp_mock_utmi_clk_src",
> >> + .parent_data = gcc_parent_data_0,
> >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> >> + .flags = CLK_SET_RATE_PARENT,
> >> + .ops = &clk_rcg2_ops,
> >
> > This is another discontinuinty with sc8280xp.
> >
> > Could you have a look through the sc8280xp gcc and do an aduit for
> > clk_rcg2_shared_ops as against sc8380xp ?
>
> ack, will do a quick audit before the re-spin.
Please trim unnecessary context from your replies. You quoted some 1400
lines of irrelevant clock structs when all you needed was something like
the above.
Not trimming replies makes it a pain to read your mails and to revisit
threads like this one, for example, in the lore web archives.
Johan
