On 15/11/2023 10:56, Jaewon Kim wrote:
> ExynosAutov920 GPIO has a different register structure.
> In the existing Exynos series, EINT control register enumerated after
> a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET).
> However, in ExynosAutov920 SoC, the register that controls EINT belongs
> to each GPIO group, and each GPIO group has 0x1000 align.
>
> This is a structure to protect the GPIO group with S2MPU in VM environment,
> and will only be applied in ExynosAuto series SoCs.
>
> Example)
> -------------------------------------------------
> | original | ExynosAutov920 |
> |-----------------------------------------------|
> | 0x0 GPIO_CON | 0x0 GPIO_CON |
> | 0x4 GPIO_DAT | 0x4 GPIO_DAT |
> | 0x8 GPIO_PUD | 0x8 GPIO_PUD |
> | 0xc GPIO_DRV | 0xc GPIO_DRV |
> | 0x700 EINT_CON | 0x18 EINT_CON |
> | 0x800 EINT_FLTCON | 0x1c EINT_FLTCON0 |
> | 0x900 EINT_MASK | 0x20 EINT_FLTCON1 |
> | 0xa00 EINT_PEND | 0x24 EINT_MASK |
> | | 0x28 EINT_PEND |
> -------------------------------------------------
>
> Pinctrl data for ExynosAutoV920 SoC.
> - GPA0,GPA1 (10): External wake up interrupt
> - GPQ0 (2): SPMI (PMIC I/F)
> - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio
> - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet
> - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose
> - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI
>
> Signed-off-by: Jaewon Kim <jaewon02.kim@xxxxxxxxxxx>
> ---
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-exynos.c | 102 ++++++++++++-
> drivers/pinctrl/samsung/pinctrl-exynos.h | 27 ++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 5 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 13 ++
> 5 files changed, 280 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..cf86722a70a3 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> .ctrl = fsd_pin_ctrl,
> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
> };
> +
> +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
> +static struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
So you created patch from some downstream code? No, please work on
upstream. Take upstream code and customize it to your needs. That way
you won't introduce same mistakes fixes years ago.
Missing const.
...
> @@ -31,6 +31,7 @@
> #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
> #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
> #define EXYNOS_SVC_OFFSET 0xB08
> +#define EXYNOSAUTOV920_SVC_OFFSET 0xF008
>
...
> #ifdef CONFIG_PINCTRL_S3C64XX
> { .compatible = "samsung,s3c64xx-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index 9b3db50adef3..cbb78178651b 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -122,6 +122,9 @@ struct samsung_pin_bank_type {
> * @eint_type: type of the external interrupt supported by the bank.
> * @eint_mask: bit mask of pins which support EINT function.
> * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
> + * @mask_offset: SoC-specific EINT mask register offset of bank.
> + * @pend_offset: SoC-specific EINT pend register offset of bank.
> + * @combine: EINT register is adjacent to the GPIO control register.
I don't understand it. Adjacent? Are you sure? GPIO control register has
0xF004 (EXYNOSAUTOV920_SVC_OFFSET + 0x4)? Anyway, this does not scale.
What if next revision comes with not-adjacent. There will be
"combine_plus"? Also name confuses me - combine means together.
Also your first map of registers does not have it adjacent...
Anyway first patch is to rework driver to support new register layout.
Second patch is to add new variant.
Best regards,
Krzysztof
