On 2023/11/15 1:31, Conor Dooley wrote:
On Mon, Nov 13, 2023 at 09:20:11PM +0800, Chen Wang wrote:
From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
Add clock generator node to device tree for SG2042, and enable clock for
uart0.
Signed-off-by: Chen Wang <unicorn_wang@xxxxxxxxxxx>
---
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++
There's no need to create an entirely new file for this.
Agree, I will merge this into sg2042.dtsi in next revision.
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 10 +++
2 files changed, 86 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
new file mode 100644
index 000000000000..66d2723fab35
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+ cgi: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "cgi";
+ #clock-cells = <0>;
+ };
What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided
by an oscillator on the board?
This oscillator is an individual ic chip outside the SoC on the board,
that's why I list it outside soc node.
Actually the "cgi" is abbrevation for "Clock Generation IC chip".
+
+ clkgen: clock-controller {
+ compatible = "sophgo,sg2042-clkgen";
+ #clock-cells = <1>;
+ system-ctrl = <&sys_ctrl>;
Why is this node not a child of the system controller?
I will move this node to child of syscon in next revision, thanks for
your reminder.
Cheers,
Conor.
