On Thu, Nov 09, 2023 at 09:50:55PM +0000, Daniel Golle wrote: > Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the > MediaTek MT7988 SoC which can operate at various interfaces modes: > > * USXGMII > * 10GBase-R > * 5GBase-R > * 2500Base-X > * 1000Base-X > * Cisco SGMII (MAC side) > > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> > --- > .../bindings/phy/mediatek,xfi-pextp.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml > new file mode 100644 > index 0000000000000..948d5031af1e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,xfi-pextp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek XFI PEXTP SerDes PHY > + > +maintainers: > + - Daniel Golle <daniel@xxxxxxxxxxxxxx> > + > +description: | Don't need '|' here. > + The MediaTek XFI PEXTP SerDes PHY provides the physical SerDes lanes > + used by the MediaTek USXGMII PCS. > + > +properties: > + $nodename: > + pattern: "^phy@[0-9a-f]+$" > + > + compatible: > + const: mediatek,mt7988-xfi-pextp > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: XFI PHY clock > + > + resets: > + items: > + - description: PEXTP reset > + > + mediatek,usxgmii-performance-errata: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R > + mode which needs a work-around in the driver. The work-around is > + enabled using this flag. > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - resets > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mediatek,mt7988-clk.h> > + #include <dt-bindings/reset/mediatek,mt7988-resets.h> > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + xfi_pextp0: phy@11f20000 { Drop unused labels. > + compatible = "mediatek,mt7988-xfi-pextp"; > + reg = <0 0x11f20000 0 0x10000>; > + clocks = <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; > + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; > + mediatek,usxgmii-performance-errata; > + #phy-cells = <0>; > + }; > + }; > + > +... > -- > 2.42.1
