As the sg2042 uses different address for timer and mswi of its clint device, it should follow the aclint format. For the previous patchs, it only use only one address for both mtime and mtimer, this is can not be parsed by OpenSBI. To resolve this, separate these two registers in the dtb. Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005738.html Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Inochi Amaoto (2): dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format .../timer/thead,c900-aclint-mtimer.yaml | 5 +- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++-------- 2 files changed, 51 insertions(+), 34 deletions(-) -- 2.42.1
