> On 01/08/2015 02:04 AM, Peter Pan 潘栋 (peterpandong) wrote:
> >>> This commit adds the devicetree binding document that specifies the
> >>> spi nand devices support.
> >>>
> >>> Signed-off-by: Peter Pan <peterpandong@xxxxxxxxxx>
> >>> ---
> >>> Documentation/devicetree/bindings/mtd/spi-nand.txt | 22
> >> ++++++++++++++++++++++
> >>> 1 file changed, 22 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/mtd/spi-
> >> nand.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/mtd/spi-nand.txt
> >> b/Documentation/devicetree/bindings/mtd/spi-nand.txt
> >>> new file mode 100644
> >>> index 0000000..9dd3efd
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/mtd/spi-nand.txt
> >>> @@ -0,0 +1,22 @@
> >>> +* NAND driver for MT29F, GD5F and similar SPI NAND flash chips
> >>> +
> >>> +Required properties:
> >>> +- #address-cells, #size-cells : Must be present if the device has
> >> sub-nodes
> >>> + representing partitions.
> >>> +- compatible : Should be the manufacturer and the name of the chip.
> >> Bear in mind
> >>>
> >>
> >> Unless I'm mistaken, we don't need the chip ID here, as SPI NAND
> allows
> >> to autodetect the device. Any reason why we can't just use a generic
> >> compatible "spi-nand" here?
> >> --
> >> Ezequiel
> >
> > In fact, I don't know how to autodetect the SPI NAND device. Micron
> device and
> > Gigadevice device have different read ID functions. The Chip ID here
> is used to
> > determine which function to use.
> >
>
> Isn't the difference between the Read ID very minor? One of the vendor
> needs a 2-byte ID read, and the other one needs a 3-byte ID read.
>
> So you can just try with 2-byte, and if that fails (no vendor ID is
> found on the first byte), you can try with the 3-byte command.
>
> It's not the most elegant solution, but it's not super awful either.
> --
> Ezequiel
I agree with your idea about try different ways to read ID. It is a better way
to detect the chip if it can work properly.
The difference between the Read ID is that some chips need to send a dummy byte
or address after opcode then read 2 byte, some chips needn't send any data after
opcode but read 3 byte.
I'm concerned maybe chip will get into unknown or vendor specified state if we
send the wrong sequence.
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