From: "jian.yang" <jian.yang@xxxxxxxxxxxx>
Add new properties to support control power supplies and reset pin of
a downstream component.
Signed-off-by: jian.yang <jian.yang@xxxxxxxxxxxx>
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index 7e8c7a2a5f9b..a4f6b48d57fa 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -84,6 +84,26 @@ properties:
items:
enum: [ phy, mac ]
+ vpcie1v8-supply:
+ description:
+ The regulator phandle that provides 1.8V power from root port to a
+ downstream component.
+
+ vpcie3v3-supply:
+ description:
+ The regulator phandle that provides 3.3V power from root port to a
+ downstream component.
+
+ vpcie12v-supply:
+ description:
+ The regulator phandle that provides 12V power from root port to a
+ downstream component.
+
+ dsc-reset-gpios:
+ description:
+ The extra reset pin other than PERST# required by a downstream component.
+ maxItems: 1
+
clocks:
minItems: 4
maxItems: 6
@@ -238,5 +258,15 @@ examples:
#interrupt-cells = <1>;
interrupt-controller;
};
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ vpcie3v3-supply = <&pcie3v3_regulator>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.18.0
