Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@xxxxxxxxxxxx>: On Fri, 29 Sep 2023 01:06:59 +0100 you wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Hi All, > > This patch series does the following: > * Adds L2 cache node and marks the SoC as noncoherent > * Enables IP blocks which were explicitly disabled and for > which support is present > * Enables the configs required for RZ/Five SoC > > [...] Here is the summary with links: - [1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node (no matching commit) - [2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property (no matching commit) - [3/5] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled (no matching commit) - [4/5] riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node (no matching commit) - [5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC https://git.kernel.org/riscv/c/db38228c03d6 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html