Cristian Ciocaltea wrote: > Provide a DT node for the SiFive Composable Cache controller found on > the StarFive JH7100 SoC. > > Note this is also used to support non-coherent DMA, via the > sifive,cache-ops cache flushing operations. This property is no longer needed: https://lore.kernel.org/linux-riscv/20231031141444.53426-1-emil.renner.berthing@xxxxxxxxxxxxx/ Also it would be nice to mention that these nodes are copied from my visionfive patches ;) > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx> > --- > arch/riscv/boot/dts/starfive/jh7100.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi > index 06bb157ce111..a8a5bb00b0d8 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi > @@ -32,6 +32,7 @@ U74_0: cpu@0 { > i-tlb-sets = <1>; > i-tlb-size = <32>; > mmu-type = "riscv,sv39"; > + next-level-cache = <&ccache>; > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > @@ -60,6 +61,7 @@ U74_1: cpu@1 { > i-tlb-sets = <1>; > i-tlb-size = <32>; > mmu-type = "riscv,sv39"; > + next-level-cache = <&ccache>; > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > @@ -147,6 +149,18 @@ soc { > dma-noncoherent; > ranges; > > + ccache: cache-controller@2010000 { > + compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache"; > + reg = <0x0 0x2010000 0x0 0x1000>; > + interrupts = <128>, <130>, <131>, <129>; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <2048>; > + cache-size = <2097152>; > + cache-unified; > + sifive,cache-ops; > + }; > + > clint: clint@2000000 { > compatible = "starfive,jh7100-clint", "sifive,clint0"; > reg = <0x0 0x2000000 0x0 0x10000>; > -- > 2.42.0 >
