Yo, On Sun, Oct 29, 2023 at 09:35:00AM -0300, Daniel Henrique Barboza wrote: > Following the examples of cbom-block-size and cboz-block-size, > cbop-block-size is the cache size of Zicbop (cbo.prefetch) operations. > The most common case is to have all cache block sizes to be the same > size (e.g. profiles such as rva22u64 mandates a 64 bytes size for all > cache operations), but there's no specification requirement for that, > and an implementation can have different cache sizes for each operation. > > Cc: Rob Herring <robh@xxxxxxxxxx> > Cc: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Signed-off-by: Daniel Henrique Barboza <dbarboza@xxxxxxxxxxxxxxxx> Firstly, odd CC list. Please CC the output of get_maintainer.pl in the future. IIRC, I mentioned defining this to Drew when he was add zicboz, but he didn't want to add it - although he seems to have asked you to document this. Drew, change of heart or am I not remembering correctly? I think he cited some interpretation of the spec from Andrei W that implied the Zicbop size would be the same as one of the other ones, but I cannot find that on lore atm. If Drew's okay with it, then I am too, so a conditional Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Cheers, Conor. > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 97e8441eda1c..1660b296f7de 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -78,6 +78,11 @@ properties: > description: > The blocksize in bytes for the Zicbom cache operations. > > + riscv,cbop-block-size: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The blocksize in bytes for the Zicbop cache operations. > + > riscv,cboz-block-size: > $ref: /schemas/types.yaml#/definitions/uint32 > description: > -- > 2.41.0 > >
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