On Fri, Oct 27, 2023 at 9:35 AM Niklas Cassel <Niklas.Cassel@xxxxxxx> wrote: > > Hello Rob, > > On Thu, Oct 26, 2023 at 01:35:01PM -0500, Rob Herring wrote: > > On Wed, Oct 25, 2023 at 08:02:32PM +0000, Niklas Cassel wrote: > > > Hello Conor, > > > > > > On Tue, Oct 24, 2023 at 05:29:28PM +0100, Conor Dooley wrote: > > > > On Tue, Oct 24, 2023 at 05:10:08PM +0200, Niklas Cassel wrote: > > > > > From: Niklas Cassel <niklas.cassel@xxxxxxx> > > > > > > > > > > Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml > > > > > using: > > > > > > > > > > allOf: > > > > > - $ref: /schemas/pci/snps,dw-pcie.yaml# > > > > > > > > > > and snps,dw-pcie.yaml does have the atu property defined, in order to be > > > > > able to use this property, while still making sure 'make CHECK_DTBS=y' > > > > > pass, we need to add this property to rockchip-dw-pcie.yaml. > > > > > > > > > > Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxx> > > > > > --- > > > > > Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++++ > > > > > 1 file changed, 4 insertions(+) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > > > index 1ae8dcfa072c..229f8608c535 100644 > > > > > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > > > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > > > > @@ -29,16 +29,20 @@ properties: > > > > > - const: rockchip,rk3568-pcie > > > > > > > > > > reg: > > > > > + minItems: 3 > > > > > items: > > > > > - description: Data Bus Interface (DBI) registers > > > > > - description: Rockchip designed configuration registers > > > > > - description: Config registers > > > > > + - description: iATU registers > > > > > > > > Is this extra register only for the ..88 or for the ..68 and for the > > > > ..88 models? > > > > > > Looking at the rk3568 Technical Reference Manual (TRM): > > > https://dl.radxa.com/rock3/docs/hw/datasheet/Rockchip%20RK3568%20TRM%20Part2%20V1.1-20210301.pdf > > > > > > The iATU register register range exists for all 3 PCIe controllers > > > found on the rk3568. > > > > > > This register range is currently not defined in the rk3568.dtsi, so the driver > > > will currently use the default register offset (which is correct), but with > > > the driver fallback register size that is only big enough to cover 8 inbound > > > and 8 outbound iATUs (internal Address Translation Units). > > > > We should probably make the driver smarter instead or in addition. We > > have the DBI size, Just make atu_size = dbi_size - DEFAULT_DBI_ATU_OFFSET. > > I though about that, but it seems that some drivers don't use > res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi") > > but instead set pci->dbi_base from non-common code, e.g.: > drivers/pci/controller/dwc/pci-dra7xx.c: pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics"); > drivers/pci/controller/dwc/pci-dra7xx.c: pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics"); > drivers/pci/controller/dwc/pci-imx6.c: pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); > drivers/pci/controller/dwc/pci-keystone.c: pci->dbi_base = base; > drivers/pci/controller/dwc/pci-layerscape-ep.c: dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); > drivers/pci/controller/dwc/pci-layerscape-ep.c: pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); > drivers/pci/controller/dwc/pci-layerscape.c: dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); > drivers/pci/controller/dwc/pci-layerscape.c: pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); > drivers/pci/controller/dwc/pci-meson.c: pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); > drivers/pci/controller/dwc/pcie-al.c: void __iomem *dbi_base = pcie->dbi_base; > drivers/pci/controller/dwc/pcie-al.c: al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res); > drivers/pci/controller/dwc/pcie-armada8k.c: pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); > drivers/pci/controller/dwc/pcie-designware.c: pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); > drivers/pci/controller/dwc/pcie-histb.c: pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc-dbi"); > drivers/pci/controller/dwc/pcie-qcom-ep.c: pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); > drivers/pci/controller/dwc/pcie-tegra194-acpi.c: pcie_ecam->dbi_base = cfg->win + SZ_512K; > > So I don't think that we can always get the size of the dbi. > And a solution that does not work for all platforms is not > that appealing. Do I get a chance to respond before you send a new version? Does something like the patch below not work for everyone? We could store the DBI size as well if we want more than 8 regions to work without a 'dbi' nor 'atu' region defined. We shouldn't have new users doing that though. diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f40b85..3dc71ea7fa76 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -105,11 +105,13 @@ int dw_pcie_get_resources(struct dw_pcie *pci) struct platform_device *pdev = to_platform_device(pci->dev); struct device_node *np = dev_of_node(pci->dev); struct resource *res; + size_t dbi_size = DEFAULT_DBI_ATU_OFFSET + SZ_4K; int ret; if (!pci->dbi_base) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); + dbi_size = resource_size(res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); } @@ -136,13 +138,10 @@ int dw_pcie_get_resources(struct dw_pcie *pci) return PTR_ERR(pci->atu_base); } else { pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + pci->atu_size = dbi_size - DEFAULT_DBI_ATU_OFFSET; } } - /* Set a default value suitable for at most 8 in and 8 out windows */ - if (!pci->atu_size) - pci->atu_size = SZ_4K; - /* eDMA region can be mapped to a custom base address */ if (!pci->edma.reg_base) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
