Hey Emil, On Wed, Oct 25, 2023 at 11:56:41AM -0700, Emil Renner Berthing wrote: > This cache controller also supports flushing cache lines by writing > their address to a register. This can be used for cache management on > SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension > such as the StarFive JH7100 SoC. I'm not really sure why we need the flag, is it not sufficient to register the cache ops on a per-compatible basis? At least for the jh7110, you're always going to want them, otherwise your system is going to be largely non-functional, right? > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > index 7e8cebe21584..36ae6f48ce0b 100644 > --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml > @@ -81,6 +81,11 @@ properties: > The reference to the reserved-memory for the L2 Loosely > Integrated Memory region. > The reserved memory node should be defined as per the bindings > in reserved-memory.txt. > > + sifive,cache-ops: > + type: boolean > + description: | and this | is not required btw, since there's no formatting here that would need to be preserved. Cheers, Conor. > + Use this cache controller for non-standard cache management operations. > + > allOf: > - $ref: /schemas/cache-controller.yaml# > > -- > 2.40.1
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