Hi Conor, On Mon, Oct 23, 2023 at 01:03:53PM +0100, Conor Dooley wrote: > On Mon, Oct 23, 2023 at 08:40:57AM +0800, Yu Chien Peter Lin wrote: > > Document the ISA string for Andes Technology performance monitor > > extension which provides counter overflow interrupt and mode > > filtering mechanisms. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx> > > --- > > Changes v2 -> v3: > > - New patch > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 5e9291d258d5..e0694e2adbc2 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -246,6 +246,13 @@ properties: > > in commit 2e5236 ("Ztso is now ratified.") of the > > riscv-isa-manual. > > > > + - const: xandespmu > > + description: > > + The Andes Technology performance monitor extension for counter overflow > > + and privilege mode filtering. For more details, see Counter Related > > + Registers in the AX45MP datasheet. > > + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > Does/will this PMU function identically on the other CPUs that support it? Yes, I can confirm that. Thanks for the review. Best regards, Peter Lin > I assume the answer is yes. > > Cheers, > Conor. > > > + > > - const: xtheadpmu > > description: > > The T-Head performance monitor extension for counter overflow. For more > > -- > > 2.34.1 > >