Quoting Sebastian Reichel (2023-10-25 12:48:49) > Hello Stephen, > > On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote: > > Quoting Elaine Zhang (2023-10-18 00:01:40) > > > Recent Rockchip SoCs have a new hardware block called Native Interface > > > Unit (NIU), which gates clocks to devices behind them. These effectively > > > need two parent clocks. > > > Use GATE_LINK to handle this. > > > > Why can't pm clks be used here? The qcom clk driver has been doing that > > for some time now. > > > > $ git grep pm_clk_add -- drivers/clk/qcom/ > > Maybe I'm mistaken, but as far as I can tell this is adding the > dependency on controller level and only works because Qualcomm > has multiple separate clock controllers. In the Rockchip design > there is only one platform device. > > Note, that the original downstream code from Rockchip actually used > pm_clk infrastructure by moving these clocks to separate platform > devices. I changed this when upstreaming the code, since that leaks > into DT and from DT point of view there should be only one clock > controller. > Why can't the rockchip driver bind to a single device node and make sub-devices for each clk domain and register clks for those? Maybe it can use the auxiliary driver infrastructure to do that?
