On Wed, Oct 25, 2023 at 08:48:57AM +0800, Chen Wang wrote: > > On 2023/10/24 16:20, Conor Dooley wrote: > > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > > > A recent submission [1] from Rob has added additionalProperties: false > > to the interrupt-controller child node of RISC-V cpus, highlighting that > > the new cv1800b DT has been incorrectly using #address-cells. > > It has no child nodes, so #address-cells is not needed. Remove it. > > > > Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@xxxxxxxxxx/ [1] > > Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree") > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Nice catch! Reviewed-by: Jisheng Zhang <jszhang@xxxxxxxxxx> > > --- > > CC: Chao Wei <chao.wei@xxxxxxxxxx> > > CC: Chen Wang <unicorn_wang@xxxxxxxxxxx> > > CC: Rob Herring <robh+dt@xxxxxxxxxx> > > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> > > CC: Paul Walmsley <paul.walmsley@xxxxxxxxxx> > > CC: Palmer Dabbelt <palmer@xxxxxxxxxxx> > > CC: Albert Ou <aou@xxxxxxxxxxxxxxxxx> > > CC: devicetree@xxxxxxxxxxxxxxx > > CC: linux-riscv@xxxxxxxxxxxxxxxxxxx > > CC: linux-kernel@xxxxxxxxxxxxxxx > > --- > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > index df40e87ee063..aec6401a467b 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > @@ -34,7 +34,6 @@ cpu0: cpu@0 { > > cpu0_intc: interrupt-controller { > > compatible = "riscv,cpu-intc"; > > interrupt-controller; > > - #address-cells = <0>; > > #interrupt-cells = <1>; > > }; > > }; > > Acked-by: Chen Wang <unicorn_wang@xxxxxxxxxxx> > > Thanks，btw, will it be merged in 6.7? Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out. > > Looping Jisheng who is working on Duo/cv1800b. >
