On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Jeff, Hi Geert, > > On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@xxxxxxxxx> wrote: >>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> wrote: >>> On Wed, 18 Oct 2023 23:27:43 +0900, >>> Geert Uytterhoeven wrote: >>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato >>>> <ysato@xxxxxxxxxxxxxxxxxxxx> wrote: >>>>> Renesas SuperH binding definition. >>>>> >>>>> Signed-off-by: Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> > >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml >>>>> @@ -0,0 +1,45 @@ >>>>> +# SPDX-License-Identifier: GPL-2.0 >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: Renesas SuperH CPUs >>>>> + >>>>> +maintainers: >>>>> + - Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> >>>>> + >>>>> +description: |+ >>>>> + The device tree allows to describe the layout of CPUs in a system through >>>>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") >>>>> + defining properties for every cpu. >>>>> + >>>>> + Bindings for CPU nodes follow the Devicetree Specification, available from: >>>>> + >>>>> + https://www.devicetree.org/specifications/ >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + items: >>>>> + - enum: >>>> >>>> Missing >>>> >>>> - jcore,j2 > >> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core. > > Compatible values do not declare any such endorsement. > >> J-Core has the responsibility for maintenance of those SH ISA compatible cores. > > The question is: does J2 implement the same instruction set as SH2, > i.e. can it run unmodified SH2 code? It can run all SH2 code, but an SH2 cannot run all J2 code. The GCC compilers we use for J2 generate J2 code, not strictly SH2 code. The main difference is SH3 dynamic shift, and (S390 derived) Compare And Swap. The new FPU is in testing now, and AFAIK there is no FPU for SH2 but I’m not sure. Cheers, J. >>>> >>>>> + - renesas,sh4 >>>> >>>> >>>>> + - const: renesas,sh >>>> >>>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to >>>> "renesas,sh", though. >>>> Is there a common base of instructions that are available on all SH cores? >>> >>> The base instruction set is sh2. >>> Before that, there is sh1, but this is not compatible with Linux. >>> I think it would be a good idea to change this to "renesas,sh2", > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
