The SM8650 Top Level Mode Multiplexer supports 211 GPIOs, and the usual UFS Reset, SDC Clk/Cmd/Data special pins. An handful of pins can have their IRQ generated by the PDC module, and for this support for the new wakeup_present & wakeup_enable_bit is required to allow the "wakeup" event to be passed to PDC and generate an interrupt or a wakeup system event. As SM8550, it also supports the i2c_pull_bit bit to enable the on-SoC load resistor for I2C busses. Dependencies: None For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm85650/upstream/integ Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> --- Neil Armstrong (3): dt-bindings: pinctrl: document the SM8650 Top Level Mode Multiplexer pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits pinctrl: qcom: Introduce the SM8650 Top Level Mode Multiplexer driver .../bindings/pinctrl/qcom,sm8650-tlmm.yaml | 157 ++ drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-msm.c | 32 + drivers/pinctrl/qcom/pinctrl-msm.h | 5 + drivers/pinctrl/qcom/pinctrl-sm8650.c | 1762 ++++++++++++++++++++ 6 files changed, 1965 insertions(+) --- base-commit: fe1998aa935b44ef873193c0772c43bce74f17dc change-id: 20231016-topic-sm8650-upstream-tlmm-4ece354ef319 Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
