Hi Anup, On Mon, Oct 23, 2023 at 10:57:58PM +0530, Anup Patel wrote: > The RISC-V advanced platform-level interrupt controller (APLIC) has > two modes of operation: 1) Direct mode and 2) MSI mode. > (For more details, refer https://github.com/riscv/riscv-aia) > > In APLIC MSI-mode, wired interrupts are forwared as message signaled > interrupts (MSIs) to CPUs via IMSIC. > > We extend the existing APLIC irqchip driver to support MSI-mode for > RISC-V platforms having both wired interrupts and MSIs. > > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> > --- [...] > +int aplic_msi_setup(struct device *dev, void __iomem *regs) > +{ > + const struct imsic_global_config *imsic_global; > + struct irq_domain *irqdomain; > + struct aplic_priv *priv; > + struct aplic_msicfg *mc; > + phys_addr_t pa; > + int rc; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + rc = aplic_setup_priv(priv, dev, regs); > + if (!priv) { This should check rc instead of priv. > + dev_err(dev, "failed to create APLIC context\n"); > + return rc; > + } > + mc = &priv->msicfg; > + > + /* > + * The APLIC outgoing MSI config registers assume target MSI > + * controller to be RISC-V AIA IMSIC controller. > + */ > + imsic_global = imsic_get_global_config(); > + if (!imsic_global) { > + dev_err(dev, "IMSIC global config not found\n"); > + return -ENODEV; For all error return paths, priv should be freed. Thanks, Sunil
