On 2023/10/21 2:01, Krzysztof Kozlowski wrote: > On 20/10/2023 12:37, William Qiu wrote: >> Add documentation to describe OpenCores Pulse Width Modulation >> controller driver. >> >> Signed-off-by: William Qiu <william.qiu@xxxxxxxxxxxxxxxx> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > Please point me where this patch got review? > This is my mistake. After making extensive changes, the tag should have been deleted Best regards, William >> Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> >> --- >> .../bindings/pwm/opencores,pwm-ocores.yaml | 53 +++++++++++++++++++ >> 1 file changed, 53 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml >> new file mode 100644 >> index 000000000000..0f6a3434f155 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml >> @@ -0,0 +1,53 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/opencores,pwm-ocores.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: OpenCores PWM controller >> + >> +maintainers: >> + - William Qiu <william.qiu@xxxxxxxxxxxxxxxx> >> + >> +description: >> + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, the PTC core >> + generates binary signal with user-programmable low and high periods. All PTC counters and >> + registers are 32-bit. >> + >> +allOf: >> + - $ref: pwm.yaml# >> + >> +properties: >> + compatible: >> + enum: >> + - opencores,pwm-ocores > > NAK. This is not something which received my review. > > > Best regards, > Krzysztof >
