Hi Krzysztof.
On 7/9/2023 11:11 PM, Krzysztof Kozlowski wrote:
On 08/07/2023 09:28, Jishnu Prakash wrote:
The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
with all SW communication to ADC going through PMK8550 which
communicates with other PMICs through PBS. One major difference is
that the register interface used here is that of an SDAM present on
...
+static int adc5_gen3_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0) {
+ dev_err(adc->dev, "Failed to get SDAM%d irq, ret=%d\n", i, irq);
+ return irq;
return dev_err_probe
Will update it in the next patchset
+ }
+ adc->base[i].irq = irq;
+
+ scnprintf(buf, sizeof(buf), "adc-sdam%d", i);
+ adc->base[i].irq_name = devm_kstrdup(adc->dev, buf, GFP_KERNEL);
+ if (!adc->base[i].irq_name)
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(pdev, adc);
+
+ init_completion(&adc->complete);
+ mutex_init(&adc->lock);
+
+ ret = adc5_get_fw_data(adc);
+ if (ret < 0) {
+ dev_err(adc->dev, "adc get dt data failed, ret=%d\n", ret);
return dev_err_probe
Will update it in the next patchset
+ return ret;
+ }
+
+ for (i = 0; i < adc->num_sdams; i++) {
+ ret = devm_request_irq(dev, adc->base[i].irq, adc5_gen3_isr,
+ 0, adc->base[i].irq_name, adc);
+ if (ret < 0) {
+ dev_err(adc->dev, "Getting IRQ %d failed, ret=%d\n", adc->base[i].irq, ret);
return dev_err_probe
Will update it in the next patchset
+ return ret;
+ }
+ }
+
+ ret = adc_tm_register_tzd(adc);
+ if (ret < 0)
+ return ret;
+
+ if (adc->n_tm_channels)
+ INIT_WORK(&adc->tm_handler_work, tm_handler_work);
+
+ indio_dev->name = pdev->name;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &adc5_gen3_info;
+ indio_dev->channels = adc->iio_chans;
+ indio_dev->num_channels = adc->nchannels;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static int adc5_gen3_exit(struct platform_device *pdev)
+{
+ struct adc5_chip *adc = platform_get_drvdata(pdev);
+ u8 data = 0;
+ int i, sdam_index;
+
+ mutex_lock(&adc->lock);
+ /* Disable all available channels */
+ for (i = 0; i < adc->num_sdams * 8; i++) {
+ sdam_index = i / 8;
+ data = MEAS_INT_DISABLE;
+ adc5_gen3_write(adc, sdam_index, ADC5_GEN3_TIMER_SEL, &data, 1);
+
+ /* To indicate there is an actual conversion request */
+ data = ADC5_GEN3_CHAN_CONV_REQ | (i - (sdam_index * 8));
+ adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &data, 1);
+
+ data = ADC5_GEN3_CONV_REQ_REQ;
+ adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &data, 1);
+ }
+
+ mutex_unlock(&adc->lock);
+
+ if (adc->n_tm_channels)
+ cancel_work_sync(&adc->tm_handler_work);
+
+ return 0;
+}
+
+static struct platform_driver adc5_gen3_driver = {
+ .driver = {
+ .name = "qcom-spmi-adc5-gen3",
+ .of_match_table = adc5_match_table,
+ },
+ .probe = adc5_gen3_probe,
+ .remove = adc5_gen3_exit,
+};
+module_platform_driver(adc5_gen3_driver);
+
+MODULE_ALIAS("platform:qcom-spmi-adc5-gen3");
Drop alias. If you need it, it means you screwed ID tables or your DTS.
Best regards,
Krzysztof
OK, I guess it's not needed, will drop it in the next patchset.
Thanks,
Jishnu
