On Fri, Oct 20, 2023 at 03:21:15PM +0100, Conor Dooley wrote: > Krzysztof, William, > > On Fri, Oct 20, 2023 at 06:37:38PM +0800, William Qiu wrote: > > Add documentation to describe OpenCores Pulse Width Modulation > > controller driver. > > > > Signed-off-by: William Qiu <william.qiu@xxxxxxxxxxxxxxxx> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> > > --- > > .../bindings/pwm/opencores,pwm-ocores.yaml | 53 +++++++++++++++++++ > > 1 file changed, 53 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml > > > > diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml > > new file mode 100644 > > index 000000000000..0f6a3434f155 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml > > @@ -0,0 +1,53 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pwm/opencores,pwm-ocores.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: OpenCores PWM controller > > + > > +maintainers: > > + - William Qiu <william.qiu@xxxxxxxxxxxxxxxx> > > + > > +description: > > + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, the PTC core > > + generates binary signal with user-programmable low and high periods. All PTC counters and > > + registers are 32-bit. > > + > > +allOf: > > + - $ref: pwm.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - opencores,pwm-ocores > > What does the extra "ocores" suffix add, when it just repeats the vendor > prefix? > > > + - starfive,jh71x0-pwm > > Krzysztof, did you approve this generic compatible? > > And the whole thing looks like it should really be something like > > items: > - enum: > - starfive,jh7100-pwm > - starfive,jh7110-pwm > - const: opencores,pwm (assuming that the opencores,pwm compatible represents a subset of what is implemented on the jh7100 series)
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