On Fri, Oct 20, 2023 at 09:00:03AM +0200, Krzysztof Kozlowski wrote: > On 19/10/2023 15:59, Yu Chien Peter Lin wrote: > > Add "andestech,cpu-intc" compatible string for Andes INTC which > > provides Andes-specific IRQ chip functions. > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx> > > --- > > Changes v1 -> v2: > > - New patch > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index 97e8441eda1c..5b216e11c69f 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -99,7 +99,9 @@ properties: > > const: 1 > > > > compatible: > > - const: riscv,cpu-intc > > + enum: > > + - riscv,cpu-intc > > + - andestech,cpu-intc > > Keep alphabetical order. Do not add stuff to the end of the lists. This > is a generic rule. Everywhere. Hi Krzysztof, Thansk for pointing this out. Will fix this in PATCH v3. Best regards, Peter Lin > Best regards, > Krzysztof >
