On Wed, Oct 11, 2023 at 07:04:56PM +0800, Minda Chen wrote:
> For bridge address base is common PLDA field, Add this
> to struct mc_pcie first.
>
> INTx and MSI codes interrupts codes will get the bridge base
> address from port->bridge_addr. For these codes will be
> changed to common codes. axi_base_addr is Microchip its own
> data.
>
> Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx>
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Thanks,
Conor.
> ---
> .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++-----------
> 1 file changed, 9 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c
> index a34ec6aad4be..60870ee1f1c9 100644
> --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> @@ -195,6 +195,7 @@ struct mc_pcie {
> struct irq_domain *event_domain;
> raw_spinlock_t lock;
> struct mc_msi msi;
> + void __iomem *bridge_addr;
> };
>
> struct cause {
> @@ -339,8 +340,7 @@ static void mc_handle_msi(struct irq_desc *desc)
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct device *dev = port->dev;
> struct mc_msi *msi = &port->msi;
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> unsigned long status;
> u32 bit;
> int ret;
> @@ -365,8 +365,7 @@ static void mc_handle_msi(struct irq_desc *desc)
> static void mc_msi_bottom_irq_ack(struct irq_data *data)
> {
> struct mc_pcie *port = irq_data_get_irq_chip_data(data);
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> u32 bitpos = data->hwirq;
>
> writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
> @@ -488,8 +487,7 @@ static void mc_handle_intx(struct irq_desc *desc)
> struct mc_pcie *port = irq_desc_get_handler_data(desc);
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct device *dev = port->dev;
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> unsigned long status;
> u32 bit;
> int ret;
> @@ -514,8 +512,7 @@ static void mc_handle_intx(struct irq_desc *desc)
> static void mc_ack_intx_irq(struct irq_data *data)
> {
> struct mc_pcie *port = irq_data_get_irq_chip_data(data);
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
>
> writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
> @@ -524,8 +521,7 @@ static void mc_ack_intx_irq(struct irq_data *data)
> static void mc_mask_intx_irq(struct irq_data *data)
> {
> struct mc_pcie *port = irq_data_get_irq_chip_data(data);
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> unsigned long flags;
> u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
> u32 val;
> @@ -540,8 +536,7 @@ static void mc_mask_intx_irq(struct irq_data *data)
> static void mc_unmask_intx_irq(struct irq_data *data)
> {
> struct mc_pcie *port = irq_data_get_irq_chip_data(data);
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> unsigned long flags;
> u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
> u32 val;
> @@ -896,8 +891,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
> static int mc_pcie_setup_windows(struct platform_device *pdev,
> struct mc_pcie *port)
> {
> - void __iomem *bridge_base_addr =
> - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + void __iomem *bridge_base_addr = port->bridge_addr;
> struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
> struct resource_entry *entry;
> u64 pci_addr;
> @@ -1081,6 +1075,7 @@ static int mc_host_probe(struct platform_device *pdev)
> mc_disable_interrupts(port);
>
> bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> + port->bridge_addr = bridge_base_addr;
>
> /* Allow enabling MSI by disabling MSI-X */
> val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);
> --
> 2.17.1
>
>
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